Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies

Cadence announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence digital and analog/custom design solutions for the latest Intel 18A process design kit(PDK). 

These advancements are being showcased today at Intel Foundry Direct Connect, underscoring Cadence’s continued leadership in driving industry innovation for artificial intelligence and machine learning(AI/ML), high-performance computing(HPC) and advanced mobility applications through its strategic partnership with Intel Foundry.

Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. 

With this collaboration, joint customers can achieve exceptional power, performance and area(PPA) efficiencies, accelerating time to market for cutting-edge system-on-chip(SoC) designs.

Cadence’s expanded portfolio also includes a range of design IP already available in the Intel 18A technology family: 112G Extended Long-Reach SerDes with superior bit error rate(BER) performance for robust data integrity over longer distances; 64G MP PHY for PCIe 6.0, CXL 3.0 and 56G Ethernet; LPDDR5X/5 – 8533 Mbps with multi-standard support; and UCIe 1.0 16G for advanced packaging. 

Mutual customers now have a broad range of IP options for their AI/ML, HPC and mobility applications leveraging Intel 18A/18A-P RibbonFET and PowerVia implementation.

In addition to the new IP for Intel 18A and 18A-P technologies, Cadence’s comprehensive suite of AI-driven design and analog/custom design solutions has been certified for the latest Intel 18A node PDK. 

This includes the complete AI-driven Cadence RTL-to-GDS flow, featuring a range of robust solutions such as the Cadence Cerebrus Intelligent Chip Explorer, Genus Synthesis Solution, Innovus Implementation System, Quantus Extraction Solution, Quantus Field Solver, Tempus Timing Solution and Pegasus Verification System. 

The flow also includes custom IC design solutions such as Cadence Virtuoso Studio, the integrated Spectre Platform and the Voltus-XFi Custom Power Integrity Solution.

Meanwhile, Cadence and Intel Foundry are engaging in early design technology co-optimization for Intel 14A-E to establish the readiness of Cadence EDA flows for the next-generation advanced node.

“Cadence is at the forefront of facilitating next-generation AI, HPC and mobility designs with Intel 18A and 18A-P technologies, and our collaboration ensures that our mutual customers can leverage our robust design IP and AI-driven digital and analog/custom solutions for unparalleled performance and efficiency,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. 

“Our expanded design IP portfolio for Intel Foundry builds on our commitment to delivering best-in-class silicon solutions, and our advanced implementations of leading standards are key to achieving scalable, high-performance designs. We look forward to continuing to partner with Intel Foundry to build out IP solutions for the AI factories and compute platform needs of the future as well as today.”

“As we optimize solutions through our ongoing collaboration, the combination of Cadence's innovative IP solutions and Intel 18A and 18A-P technologies delivers advantages for AI/ML and HPC applications,” stated Suk Lee, vice president and general manager, Ecosystem Technology Office at Intel Foundry. 

“Working together, we are accelerating the development of high-performance solutions, including for chiplets, that meet the evolving needs of the industry and empower our mutual customers to drive PPA efficiencies and accelerate time to market for their innovative next-generation SoC designs.”